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single-channel, 64-position, push button, 8% resistor tolerance, nonvolatile digital potentiometer data sheet ad5116 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features single-channel, 64-position resolution 5 k, 10 k, 80 k nominal resistance maximum 8% nominal resistor tolerance error low minimum a-w and b-w resistance feature end scale resistance indicator 2.3 v to 5.5 v single-supply operation 6 ma maximum continuous a, b, and w current density simple push button manual configurable control built-in adaptive debouncer discrete step-up/step-down control auto scan up/down control auto or manual save of wiper position power-on eeprom refresh time < 50 s rheostat mode temperature coefficient: 35 ppm/c potentiometer mode temperature coefficient: 5 ppm/c 50-year typical data retention at 125c 1 million write cycles wide operating temperature: ?40c to +125c thin, 2 mm 2 mm 0.55 mm 8-lead lfcsp package applications mechanical potentiometer replacement portable electronics level adjustment audio volume control low resolution dac lcd panel brightness and contrast control programmable voltage to current conversion programmable filters, delays, time constants feedback resistor programmable power supply sensor calibration functional block diagram adaptive debouncer control logic block eeprom rdac register ad5116 a w b data data gnd v dd v dd 09657-001 ase pu pd figure 1. general description the ad5116 provides a nonvolatile digital potentiometer solution for 64-position adjustment applications, offering guaranteed low resistor tolerance errors of 8% and up to 6 ma current density in the a, b, and w pins. the low resistor tolerance, low nominal temperature coefficient, and high bandwidth simplify open-loop applications, as well as tolerance matching applications. the new low a-w and b-w resistance feature minimizes the wiper resistance in the extremes of the resistor array to typically 45 . a simple push button interface allows manual control with just two external push button switches. the ad5116 is designed with a built-in adaptive debouncer that ignores invalid bounces due to contact bounce (commonly found in mechanical switches). the debouncer is adaptive, accommodating a variety of push buttons. the ad5116 can automatically save the last wiper position into eeprom, making it suitable for applications that require a power-up in the last wiper position, for example, audio equipment. the ad5116 is available in a 2 mm 2 mm 8-lead lfcsp package. the part is guaranteed to operate over the extended industrial temperature range of ?40c to +125c. table 1. nvm 8% resistance tolerance family model resistance (k) position interface ad5110 10, 80 128 i 2 c AD5111 10, 80 128 up/down ad5112 5, 10, 80 64 i 2 c ad5113 5, 10, 80 64 up/down ad5116 5, 10, 80 64 push button ad5114 10, 80 32 i 2 c ad5115 10, 80 32 up/down
ad5116 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 interface timing specifications .................................................. 5 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 12 theory of operation ...................................................................... 13 rdac register ............................................................................ 13 eeprom ..................................................................................... 13 automatic save enable .............................................................. 13 end scale resistance indicator ................................................. 14 rdac architecture .................................................................... 14 progr amming the variable resistor ......................................... 14 programming the potentiometer divider ............................... 15 terminal voltage operating range ......................................... 15 power - up sequence ................................................................... 15 layout and power supply biasing ............................................ 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 10 /11 revision 0: initial version
data sheet ad5116 rev. 0 | page 3 of 16 specifications electrical character istics 5 k, 10 k, and 80 k versions: v dd = 2.3 v to 5.5 v , v a = v dd , v b = 0 v , ?40c < t a < +125c, unless otherwise noted. table 2. parameter symbol test conditions /comments min typ 1 max unit dc characteristics rheostat mode r esolution n 6 bits resistor integral nonlinearity 2 r - inl r ab = 5 k?, v dd = 2.3 v to 2.7 v ? 2.5 0.5 +2.5 lsb r ab = 5 k?, v dd = 2.7 v to 5.5 v ? 1 0.25 +1 lsb r ab = 10 k? ? 1 0.25 +1 lsb r ab = 80 k? ? 0.25 0.1 +0.25 lsb resistor differential n onlinearity 2 r - dnl ? 1 0.25 +1 lsb nominal resistor tolerance r ab /r ab ? 8 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance r w code = zero scale 70 140 ? r bs code = bottom scale 45 80 ? r ts code = top scale 70 140 ? dc characteristics potentiometer divider mode integral nonlinearity 4 inl ? 0.5 0.15 +0.5 lsb differential nonlinearity 4 d nl ? 0.5 0.15 +0.5 lsb ful l - scale error v wfse r ab = 5 k? ? 2.5 lsb r ab =10 k? ? 1.5 lsb r ab = 80 k? ? 1 lsb zero - scale error v wzse r ab = 5 k? +1.5 lsb r ab =10 k? +1 lsb r ab = 80 k? +0.25 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 10 p pm/c resistor terminals maximum continuous i a , i b , and i w current 3 r ab = 5 k?, 10 k? ? 6 +6 ma r ab = 80 k? ? 1.5 +1.5 ma terminal voltage range 5 gnd v dd v capacitance a, capacitance b 3 , 6 c a , c b f = 1 mhz, measured to gnd, code = h alf scale, v w = v a = 2.5 v or v w = v b = 2.5 v 20 pf capacitance w 3 , 6 c w f = 1 mhz, measured to gnd, code = half scale, v a = v b = 2.5 v 35 pf common - mode leakage current 3 v a = v w = v b 50 na digital inputs (pu and pd) input logic 3 high v inh 2 v low v inl 0.8 v input current 3 i n 1 a input capacitance 3 c in 5 pf digital output ( ase ) output high voltage 3 v oh i si nk = 2 ma, v dd = 5 v 4.8 v output current 3 i o v dd = 5 v 16 ma three - state leakage current 3 i oz 1 a input capacitance 3 c in 5 pf
ad5116 data sheet rev. 0 | page 4 of 16 parameter symbol test conditions /comments min typ 1 max unit power supplies single - supply power range 2.3 5.5 v positive supply current i dd v dd = 5 v 750 n a eemem store current 3 , 7 i dd_nvm_store 2 ma eemem read current 3 , 8 i dd_nvm_read 320 a power dissipation 9 p diss v ih = v logic or v il = gnd 5 w power supply rejection 3 psr ? v dd / ? v ss = 5 v 10% r ab = 5 k? ? 43 db r ab =10 k? ? 50 db r ab = 80 k ? ? 64 db dynamic characteristics 3 , 10 bandwidth bw code = half scale ? 3 db r ab = 5 k? 4 mhz r ab = 10 k ? 2 mhz r ab = 80 k ? 200 khz total harmonic distortion thd v a = v dd /2 + 1 v rms, v b = v dd /2, f = 1 khz, code = half scale r ab = 5 k? ?75 db r ab = 10 k ? ?80 db r ab = 80 k ? ?85 db v w settling time t s v a = 5 v, v b = 0 v, 0.5 lsb error band r ab = 5 k? 2.5 s r ab = 10 k ? 3 s r ab = 80 k ? 10 s resistor noise density e n_wb code = half scale, t a = 25c, f = 100 khz r ab = 5 k ? 7 nv/hz r ab = 10 k ? 9 nv/hz r ab = 80 k ? 20 nv/hz flash/ee memory reliability 3 endurance 11 t a = 25 c 1 mcycles 100 kcycles data retention 12 50 years 1 typical values represent average readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 resistor position nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum resistance and the minimum resi stance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is limited to 0.8 v dd /r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl a re measured at v w b with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 r esistor t erminal a, r esistor t ermina l b, and r esistor t erminal w have no limitations on polarity with respect to each other. 6 c a is measured with v w = v a = 2.5 v, c b is measured with v w = v b = 2.5 v , and c w is measured with v a = v b = 2.5 v . 7 different from operating current; supply curren t for nvm program lasts approximately 30 ms . 8 different from operating current; supply current for nvm read lasts approximately 20 s . 9 p diss is calculated from (i dd v dd ) . 10 all dynamic characteristics use v dd = 5.5 v, and v logic = 5 v. 11 endurance is qualified at 100,000 cycles per jedec standard 22, method a117 and measured at 150 c . 12 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime based on an activation energy of 1 ev derates with junction temperature in the flash/ee memory.
data sheet ad5116 rev. 0 | page 5 of 16 interface timing specifications v dd = 2.3 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter test conditions/comments min typ max unit description t 1 8 ms debounce time t 2 1 sec manual to auto scan time t 3 140 ms auto scan step t 4 ase = 0 v, pd = gnd, pu = gnd 1 sec auto save execute time t 5 ase = v dd 8 ms low pulse time to manual storage t eeprom_program 1 15 50 ms memory program time t power_up 2 50 s power-on eeprom restore time 1 eeprom program time depends on the temper ature and eeprom write cycles. higher timing is expected at a lower temperature and h igher write cycles. 2 maximum time after v dd is equal to 2.3 v. timing diagrams 09657-002 pu r w t 1 pd (low) figure 2. manual increment mode timing 09657-003 pu t 1 t 2 t 3 pd (low) r w figure 3. auto increment mode timing 0 9657-004 pd t 1 t 4 eeprom data new data t eeprom program r w ase (low) figure 4. auto save mode timing 09657-005 pd/pu (low) t 5 eeprom data new data t eeprom program ase figure 5. manual save mode timing 09657-006 pd t 1 r w r w = 45 ? ase figure 6. end scale indication timing
ad5116 data sheet rev. 0 | page 6 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd C0.3 v to +7.0 v v a , v w , v b to gnd gnd ? 0.3 v to v dd + 0.3 v i a , i w , i b pulsed 1 frequency > 10 khz r aw = 5 k and 10 k 6 ma/d 2 r aw = 80 k 1.5 ma/d 2 frequency 10 khz r aw = 5 k and 10 k 6 ma/d 2 r aw = 80 k 1.5 ma/d 2 continuous r aw = 5 k and 10 k 6ma r aw = 80 k 1.5ma push button inputs ?0.3 v to +7 v or v dd + 0.3 v (whichever is less) operating temperature range 3 ?40c to +125c maximum junction temperature (t j max) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 pulse duty factor. 3 includes programmin g of eeprom memory. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by jedec specification jesd-51, and the value is dependent on the test board and test environment. table 5. thermal resistance package type ja jc unit 8-lead lfcsp 90 1 25 c/w 1 jedec 2s2p test board, still air (0 m/sec air flow). esd caution
data sheet ad5116 rev. 0 | page 7 of 16 pin configuration an d function descripti ons ad5 1 16 t op view (not to scale) notes 1. the exposed p ad is internal l y flo a ting. 09657-007 3 w 4 b 1 v dd 2 a 6 pd 5 gnd 8 7 pu ase figure 7 . pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 v dd positive power supply. this pin sh ould be decoupled with 0.1f ceramic capacitors and 10 f capacitors. 2 a terminal a of rdac. gnd v a v dd . 3 w wiper terminal of rdac. gnd v w v dd . 4 b terminal b of rdac. gnd v b v dd . 5 gnd ground pin. 6 pd push - down pin. connect to the external push button. active high. an internal 100 k ? pull - down resistor is con nected to gnd. 7 pu push - up pin. connect to the external push button. active high. an internal 100 k ? pull - down resistor is connected to gnd. 8 ase automatic save enable . automatic save enable is c onfigured at power -u p. active low. this pin requires a pull resistor connected between v dd or gnd. if ase is enabled, this pin also indicates when the end scale (maximum or minimum resistance) has been reached. epad exposed pad. the exposed pad is internally floating.
ad5116 data sheet rev. 0 | page 8 of 16 typ ical performance cha racteristics ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-in l (lsb) 09657-008 figure 8 . r - inl vs. code 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 code (decimal) in l (lsb) 09657-009 figure 9 . inl vs. code 09657-010 ?10 0 0 10 0 20 0 30 0 s u pp l y curr e n t ( n a ) 40 0 50 0 60 0 70 0 80 0 ?4 0 ?2 5 ?1 0 5 2 0 3 5 t emper a t ur e ( c ) 5 0 6 5 8 0 9 5 1 1 0 12 5 v d d = 2 . 3 v v d d = 3 . 3 v v d d = 5 v figure 10 . supply current vs. temperature 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 code (decimal) r-dn l (lsb) 09657-0 1 1 figure 11 . r - dnl vs. code ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) dn l (lsb) 09657-012 figure 12 . dnl vs. code 0 0.2 0.4 0.6 0.8 1.0 1.2 0.05 0.65 1.25 1.85 2.45 3.05 3.65 4.25 4.85 digital input voltage (v) supply current (ma) v dd = 5v v dd = 3.3v v dd = 2.3v t a = 2 5 c 09657-013 figure 13 . supply current ( i dd ) vs. digital input voltage
data sheet ad5116 rev. 0 | page 9 of 16 0 ? 60 ? 50 ?4 0 ?3 0 ?2 0 ?1 0 1 00m 10 m 1 m 10 0k 1 0k gain (db) frequency (hz) 0x20 0x10 0x08 0x04 0x02 0x01 0x00 09657-014 figure 14 . 5 k? gain vs. frequency vs. code ?6 0 ?5 0 ?4 0 ?3 0 ?1 0 0 1 0k 1 m 100 k gain (db) f r e q u e nc y ( h z) ?2 0 ? 80 ?7 0 0x20 0x08 0x02 0x01 0x04 0x00 0x10 09657-015 figure 15 . 80 k? gain vs. frequency vs. code 0 20 40 60 80 100 120 140 160 180 200 10k ? 80k ? 5k ? v dd = 5v rheostat mode tempco (ppm/c) code (decimal) 0 10 20 30 40 50 60 09657-016 figure 16 . rheostat mode tempco r wb / t vs. code ?5 0 ?4 0 ?3 0 ?1 0 0 1m 10m 100k 10k gain (db) frequency (hz) ?2 0 ? 70 ?6 0 0x20 0x08 0x02 0x01 0x04 0x00 0x10 09657-017 figure 17 . 10 k? gain vs. frequency vs. code ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 100k 1m 10m phase (degrees) frequenc y (hz) full scale half scale quarter scale r ab = 10k? 09657-018 figure 18 . normalized phase flatness vs. frequency 0 20 40 60 80 100 120 140 160 180 200 potentiometer mode tempco (ppm/c) 10k? 80k? 5k? v dd = 5v code (decimal) 0 10 20 30 40 50 60 09657-019 figure 19 . potentiometer mode tempco r wb / t vs. code
ad5116 data sheet rev. 0 | page 10 of 16 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 thd + n (db) frequenc y (hz) 20 200 2k 20k 200k 10k 5k 80k 09657-020 v dd = 5v v a = 2.5v + 1v rms v b = 2.5v code = half scale noise filter = 22khz figure 20 . total harmonic distortion + noise (thd + n) vs. frequency 0 10 20 30 40 50 60 70 bandwidth (mhz) 80 5k + 250pf 10k + 75pf 10k + 150pf 10k + 250pf 80k + 0pf 80k + 75pf 80k + 150pf 80k + 250pf 5k + 0pf 5k + 75pf 5k + 150pf 10k + 0pf code (decimal) 0 10 20 30 40 50 60 09657-021 figure 21 . max imum bandwidth vs. code vs. net capacitance 0 30 60 90 incremental wiper on resistance ( ?) 120 150 0 1 2 3 v dd (v) 4 5 6 5.5v 5v 3.3v 2.7v 2.3v t a = 25c 09657-022 figure 22 . incremental wiper on resistance vs. v dd thd + n (db) amplitude (v rms) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.001 0.01 0.1 1 10k 5k 80k 09657-023 v dd = 5v v a = 2.5v + v in v b = 2.5v f in = 1khz code = half scale noise fi l ter = 22khz figure 23 . total harmonic distortion + noise (thd + n) vs. amplitude ?0.10 ?0.05 0 0.05 0.10 0.15 rel a tive vo lt age (v) 0.20 0.25 0.30 0.35 ?1 1 3 5 time (s) 7 9 5k ? 10k ? 80k ? v dd = 5v v a = v dd v b = gnd 09657-024 figure 24 . maximum transition glitch 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.0005 0.0010 0.0015 0.0020 0.0025 ?400 ?500 ?600 ?300 ?200 ?100 0 100 200 300 400 500 600 cumul a tive probabilit y probabilit y densit y resis t or drift (ppm) 09657-047 figure 25 . resistor lifet ime drift
data sheet ad5116 rev. 0 | page 11 of 16 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequenc y (hz) psrr (db) 10 100 1k 10k 100k 1m 5k ? 10k ? 80k ? 09657-026 v dd = 5v 10% ac v a = 4v v b = gnd half scale t a = 25c figure 26 . power supply rejection ratio (psrr) v s. frequency ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 10k? 80k? 5k? 2.5 0.6 1.2 1.8 0 voltage (mv) time (s) v dd = 5v v a = v dd v b = gnd 09657-027 figure 27 . digital feedthrough ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 1m 10m gain (db) frequenc y (hz) 5k ? 10k ? 80k ? 09657-028 figure 28 . shutdown isolation vs. frequency 0 1 2 3 4 5 6 7 theoretica l i max (ma) 10k ? 80k ? 5k ? code (decimal) 0 10 20 30 40 50 60 09657-029 figure 29 . theoretical maximum current vs. code 0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 current (ma) v dd (v) t a = 25c 09657-044 figure 30 . maximum ase output current vs. voltage 0 1 2 3 4 5 6 7 8 ?40 ?20 0 20 40 60 80 100 120 current (ma) temper a ture (c) v dd = 3v 09657-045 figur e 31 . maximum ase output current vs. temperature
ad5116 data sheet rev. 0 | page 12 of 16 test circuits figure 32 to figure 37 define the test conditions used in the specifications section. 09657-030 a w b nc i w dut v ms nc = no connect figure 32. resistor position nonlinearity error (rheostat operation: r-inl, r-dnl) 09657-031 a w b dut v ms v+ v += v dd 1lsb = v+/2 n figure 33. potentiometer divider nonlinearity error (inl, dnl) 09657-032 + ? dut 0.1v = 0.1v i wb i wb w b nc = no connect r w a nc gnd to v dd figure 34. wiper resistance 09657-033 a w b v ms ~ v a v dd v+ v+=v dd 10% ? v ms % ? v dd % pss (%/%) = psrr (db) = 20 log ? v ms ? v dd figure 35. power supply sensitivity (pss, psrr) 09657-034 o ffset gnd a b dut w +15 v v in v out op42 ?15v 2.5v figure 36. gain and phase vs. frequency 09657-035 dut i cm w b v dd gnd a v dd gnd gnd v dd gnd v dd figure 37. common-mode leakage current
data sheet ad5116 rev. 0 | page 13 of 16 theory of operation the ad5116 digital programmable resistor is designed to operate as a true variable resistor for analog signals within the terminal voltage range of gnd < v term < v dd . the resistor wiper position is d etermined by the rdac register contents. the rdac register is a standard logic register; there is no restriction on the number of changes allowed. the rdac register can be programmed with any position setting using the push b utton interface. once a desirab le wiper position is found, this value can be stored in the eeprom memory. thereafter, the wiper position is always restored to that position for subsequent power - up. the storing of eeprom data takes approximately 20 ms; during this time, the device is lo cked and does not accept any new operation , thus preventing any changes from taking place. the ad5116 is designed to support external push buttons (tactile switches) directly, as shown in figure 1 . rdac register the rdac register directly controls the position of the digital potentiometer wiper. for example, when the rdac register is 0x20, the wiper is connected to midscale of the variable resistor. the rdac register is controlled using the pd and pu push buttons. the step - up and step - down operations require the activation of the pu (push - up) and pd (push - down) pins. these pins have 100 k internal pull - up resistors that pu and pd activate at logic high. the follo w ing paragraphs explain how to in crement the rdac register , but all the descriptions are valid to de crement the rdac register , swapping pu by pd. manual in crement the ad5116 features an adaptive debouncer that monitors the duration of the logic high level of pu signal between bounces. if the pu logic high level signal duration is shorter than 8 ms, the de bouncer ignores it as an invalid incrementing command. whenever the logic high level of pu signal lasts longer than 8 ms, the debouncer assumes that the last bounce is met and , therefore , increments the rdac register by one step. the wiper is increment ed b y one tap position, as shown in figure 2 . auto scan increment if the pu button is held for longer than 1 second, continuously holdin g it activates auto scan mode , and the ad5116 in cremen ts the rdac register by one step every 140 ms until pu is released. typical timing is shown in figure 3 . low wiper resistance feature the ad5116 includes extra steps to achieve a minimu m wiper resistance. between terminal w and terminal b, this extra step is called bottom scale and the wiper resistance decreases from 70 ? to 45 ?. between terminal a and terminal w , this extra step is called top scale and connects the a and w terminals, r educing the 1 lsb resistor typical at full - scale code. these new extra steps are loaded automatically in the rdac register after zero - scale or full - scale position has been reached. the extra steps are not equal to 1 lsb , and are not included in the inl, dn l, r - inl, and r - dnl specifications. whenever the minimum r wb (= r bs ) is reached, the resistance stops decrementing. any continuous holding of the pd to logic high simply elevates the supply current. when r aw reaches the minimum resistance (= r ts ), continuo us holding of pu only elevates the supply current. eeprom the ad5116 contains an eeprom memory that allows wiper position storage. once a desirable wiper position is found, this value can be saved into the eepro m. thereafter , the wiper position will always be set at that position for any future on - off - on power supply sequence. automatic save enabl e at power - up, the ad5116 checks the level in the ase p in. if the pin is pulled low , as shown in figure 38 , the automatic store is enabled. if the pin is pulled high , as shown in figure 39, automatic store is disabled and the rdac register should be stored ma nually. during the storage cycle, the device is locked and does not accept any new operation preventing any changes from taking place. 09657-036 ad5 1 16 100k ? ase gnd figure 38 . automatic store enables auto save if there is no activity on inputs during 1 second , the ad5116 stores the rdac register data into eeprom, as shown in figure 4 . manual store the storage is controlled by the ase pin , which is connected to an adaptive d ebouncer. if the ase pin is pulled low longer than 8 ms , the ad5116 saves the rdac register data into eeprom, as shown in figure 5 . 09657-037 ad5 1 16 100k ? ase v dd v dd figure 39 . automatic store disables w ith manual storage push button
ad5116 data sheet rev. 0 | page 14 of 16 end scale resistance indicator when the auto save mode is enabled, the ase pin also indicates when the rdac register reaches the maximum or minimum scale. the ad5116 pulls the ase pin high and holds it as long as pd or pu is active, and the part is placed in the end scale resistance (r ts or r bs ), as shown in figure 6. the typical pin configuration is shown in figure 40. when the part is placed at the end of the resistance scale (r ts or r bs ), the ase pin is pulled high during the debounce time, until the rdac register is incremented (r bs ) or decremented (r ts ) by activating pu or pd. 0 9657-038 ad5116 100k ? ase gnd figure 40. typical end scale indicator circuit rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5116 employs a two-stage segmentation approach as shown in figure 41. the ad5116 wiper switch is designed with the transmission gate cmos topology and with the gate voltage derived from v dd . 09657-039 r w s w w r w 6-bit address decoder a ts bs r l r l b r l r l figure 41. simplifi ed rdac circuit top scale/bottom scale architecture in addition, the ad5116 includes a new feature to reduce the resistance between terminals. these extra steps are called bottom scale and top scale. at bottom scale, the typical wiper resistance decreases from 70 to 45 . at top scale, the resistance between terminal a and terminal w is decreased by 1 lsb and the total resistance is reduced to 70 . the extra steps are not equal to 1 lsb and are not included in the inl, dnl, r-inl, and r-dnl specifications. programming the variable resistor rheostat operation8% resistor tolerance the ad5116 operates in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be floating or tied to the w terminal as shown in figure 42. 09657-040 w a b w a b w a b figure 42. rheostat mode configuration t h e nom i n a l re s i st anc e b e t we e n te r m i n a l a a n d te r m i n a l b, r ab , is available in 5 k, 10 k, and 80 k and has 64 tap points accessed by the wiper terminal. the 6-bit data in the rdac latch is decoded to select one of the 64 possible wiper settings. the general equation for determining the digitally programmed output resistance between the w terminal and b terminal is: bs wb rr ? bottom scale (1) w ab wb rr d dr ??? 64 )( from 0 to 64 (2) where: d is the decimal equivalent of the binary code in the 6-bit rdac register. r ab is the end-to-end resistance. r bs is the wiper resistance at bottom scale. similar to the mechanical potentiometer, the resistance of the rdac between the w terminal and the a terminal also produces a digitally controlled complementary resistance, r wa . r wa starts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equation for this operation is: w ab aw rrr ? ? bottom scale (3) w ab aw rr d dr ?? ? ? 64 64 )( from 0 to 63 (4) ts aw rr ? top scale (5) where: d is the decimal equivalent of the binary code in the 6-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance. r ts is the wiper resistance at top scale. regardless of which setting the part is operating in, take care to limit the current between the a terminal to b terminal, w terminal to a terminal, and w terminal to b terminal, to the maximum continuous current or pulsed current specified in table 4. otherwise, degradation or possible destruction of the internal switch contact can occur.
data sheet ad5116 rev. 0 | page 15 of 16 programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper-to-b and wiper-to-a that is proportional to the input voltage at a to b, as shown in figure 43. unlike the polarity of v dd to gnd, which must be positive, voltage across a-to-b, w- to-a, and w-to-b can be at either polarity. 09657-041 w a b v in v out figure 43. potentiometer mode configuration if ignoring the effect of the wiper resistance for simplicity, connecting terminal a to 5 v and terminal b to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 5 v. the general equation defining the output voltage at v w , with respect to ground for any valid input voltage applied to terminal a and terminal b, is: b ab aw a ab wb w v r dr v r dr dv ???? )( )( ) ( (6) where: r wb (d) can be obtained from equation 1 or equation 2. r aw (d) can be obtained from equation 3 to equation 5 . operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r wa and r wb , and not the absolute values. therefore, the temperature drift reduces to 5 ppm/c. terminal voltage operating range the ad5116 is designed with internal esd diodes for protection. these diodes also set the voltage boundary of the terminal operating voltages. positive signals present on te r m i n a l a , te r m i n a l b, or te r m i n a l w t h at e x c e e d v dd are clamped by the forward-biased diode. there is no polarity constraint between v a , v w , and v b , but they cannot be higher than v dd or lower than gnd. power-up sequence because of the esd protection diodes that limit the voltage compliance at terminal a, terminal b, and terminal w (see figure 44), it is important to power on v dd before applying any voltage to terminal a, terminal b, and terminal w. otherwise, the diodes are forward-biased such that v dd is powered on unintentionally and can affect other parts of the circuit. similarly, v dd should be powered down last. the ideal power-on sequence is in the following order: gnd, v dd , and v a /v b /v w . the order of powering v a , v b , and v w is not important as long as they are powered on after v dd . the states of the pu and pd pins can be logic low or floating, but they should not be logic high during power-on. gnd 09657-042 v dd a w b figure 44. maximum terminal voltages set by v dd and v ss layout and power supply biasing it is always a good practice to use compact, minimum lead length layout design. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. it is also good practice to bypass the power supplies with quality capacitors. low equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and to filter low frequency ripple. figure 45 illustrates the basic supply bypassing config- uration for the ad5116. 09657-043 ad5116 c2 10f c1 0.1f v dd v dd agnd gnd + figure 45. power supply bypassing
ad5116 data sheet rev. 0 | page 16 of 16 outline dimensions 1.70 1.60 1.50 0.425 0.350 0.275 t op view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index are a 2.00 bsc sq sea ting plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.175 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07- 1 1-20 1 1-b figure 46 . 8 - lead lead frame chip scale package [lfcsp_ud] 2.00 mm 2.00 mm body, ultra thin, dual lead (cp - 8 - 10) dimensions shown in millimeters ordering guide model 1 r ab (k ? ) resolution temperature range package description package option branding code ad5116bcpz5 - rl7 5 64 ? 40c to +125c 8- lead lfcsp_u d cp -8-10 7g ad5116bcpz5 - 500r7 5 64 ? 40c to +125c 8- lead lfcsp_u d cp -8-10 7g ad5116bcpz10 - rl7 10 64 ? 40c to +125c 8 - l ead lfcsp_u d cp - 8 - 10 7f ad5116bcpz10 - 500r7 10 64 ? 40c to +125c 8- lead lfcsp_u d cp -8-10 7f ad5116bcpz80 - rl7 80 64 ? 40c to +125c 8- lead lfcsp_u d cp -8-10 7h ad5116bcpz80 - 500r7 80 64 ? 40c to +125c 8- lead lfcsp_u d cp -8-10 7h eval - ad5116sdz evaluati on board 1 z = rohs compliant part. ? 20 11 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09657 - 0- 10/11(0)

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